PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

A TCL script to extract Vivado's xsim simulation data in the VCD format packaged with a VCD converter with multiple conversion options including exporting to excel and changing the radix.

Project is a high-precision chronometer using VHDL, intended for implementation on an FPGA. The chronometer is designed to operate with nanosecond (ns) precision and is capable of accurately measuring elapsed time in milliseconds, seconds, and minutes. The design has been tested using a VHDL test bench and verified with the XSim extensively.

The PWM (Pulse Width Modulation) Generator creates a PWM signal to control PWM-driven devices. It allows configurable clock and PWM frequencies via generics. The duty cycle, input as a 7-bit signal, adjusts the proportion of time the signal is high.

HSpecID-X: A Hyperspectral Pixel Classifier Accelerator for X-HEEP

Simple UVM example with Altair (Metrics) DSim and Vivado xsim