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cmodel

Here are 2 public repositories matching this topic...

wyvernSemi / usbModel

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

usb vhdl verilog vivado systemverilog icarus-verilog ghdl nvc xsim cosimulation cmodel questa-sim

Updated Oct 15, 2024
C++

fmj95817 / rvbucket

C-Model and RTL Implementation of a 32-bit RISC-V Architecture SoC

cpu rtl mcu risc-v cmodel

Updated Dec 1, 2025
C

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