Skip to content

Pull requests: llvm/circt

New pull request New
181 Open 6,868 Closed
181 Open 6,868 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

[VerifToSMT] Consider assertions inside funcs
#9487 opened Jan 21, 2026 by TaoBi22 Loading…
1
[FIRRTL] AnnotateInputOnlyModules: Skip modules with enabled layers
#9485 opened Jan 21, 2026 by uenoku Loading…
Fix bit-select sensitivity lists leaking LLHD ops (Fixes #9469)
#9481 opened Jan 20, 2026 by 5iri Loading…
2
[MooreToCore][Moore][ImportVerilog] Add basic ops for dynamic string type ImportVerilog Moore
#9480 opened Jan 20, 2026 by KavyaChopra04 Loading…
18
[FIRRTL][OM] Add, use UnknownValueOp FIRRTL Involving the `firrtl` dialect OM Object Model
#9474 opened Jan 20, 2026 by seldridge Loading…
4
[FIRRTL] Add DomainKind attribute to WireOp for domain-typed Wires
#9453 opened Jan 14, 2026 by MrRoy09 Loading…
[InnerSymbolTable] Expose a method to add an InnerSymTarget.
#9446 opened Jan 13, 2026 by mikeurbach Loading…
5
[FIRRTL] Drop Source/Sink Annotation Support
#9429 opened Jan 8, 2026 by seldridge • Draft
1
[LLVM] try/integrate llvm/llvm-project#171775
#9402 opened Jan 3, 2026 by makslevental • Draft
2
[FIRRTL] Add folders for IntegerShrOp
#9401 opened Jan 2, 2026 by stomfaig Loading…
1
7
[LTL] Make ltl.delay clocking explicit (add %clock and <edge> operands)
#9392 opened Dec 29, 2025 by Clo91eaf • Draft
5
Avoid crash on memref.global without dense initializer
#9391 opened Dec 28, 2025 by RCoeurjoly Loading…
1
1
[FSM] Lower FSM to SMT dialect FSM the FSM dialect SMT
#9379 opened Dec 22, 2025 by luisacicolini • Draft
21
[ESI] Add type ser/de capability
#9353 opened Dec 17, 2025 by mortbopet Loading…
13
[Firtool] Add FlattenModules pass with command-line options
#9285 opened Dec 2, 2025 by prithayan Loading…
2
[HW] Add HWVectorization pass
#9222 opened Nov 10, 2025 by mafeguimaraes Loading…
9
[HW] Add HWConstProp pass for inter-module constant propagation
#9207 opened Nov 7, 2025 by prithayan Loading…
13
[RTG] Add folders for most set operations RTG Involving the `rtg` dialect
#9190 opened Nov 5, 2025 by maerhart Loading…
1
[FIRRTL] Add alternative constraint-based InferWidths pass
#9173 opened Nov 3, 2025 by wky17 Loading…
1
29
[ESI] Add missing ensureValid calls
#9137 opened Oct 24, 2025 by mortbopet Loading…
Deduplicate mulitple moore.procedure ops that with identical wait_eve…
#9101 opened Oct 16, 2025 by SimonEbner Loading…
[ESI] Add serde support for wide integers
#9091 opened Oct 14, 2025 by mortbopet Loading…
1
No custom printer for CompReg - leading to loss of quotation marks Resolves #8833 bug Something isn't working Seq Involving the `seq` dialect
#9049 opened Oct 4, 2025 by KaiS987 Loading…
1
1
fix: corner cases in aggregate generation
#9036 opened Sep 30, 2025 by tianrui-wei Loading…
6
[Synth ] feat : Fold Majority Graph
#9033 opened Sep 27, 2025 by markram1729 Loading…
25
ProTip! Mix and match filters to narrow down what you’re looking for.