Popular repositories Loading

1. Simple-RISCV Simple-RISCV Public

   A simple RV32I RISC-V processor core implemented from scratch for learning and experimentation. Includes RTL design, testbenches, and simulation setup.

   Verilog 1

2. VLSI-Asic-flow-Opensource_Procedure VLSI-Asic-flow-Opensource_Procedure Public

   Step-by-step documented flow for performing ASIC design using OpenROAD. Includes environment setup, floorplanning, placement, routing, and timing closure — with verified commands and tool versions.

   Verilog